Verified Deep Learning with Lean 4

C The ImageNet tier

Track 4 of Table A-1, the scale tier. Six networks train on full ImageNet-1k off the same certified renderer as their Imagenette counterparts, in the chapter order Track 3 uses. Every row trains on four 16 GB cards; a 12 GB card runs all but ConvNeXt-B and ViT-B, whose steps peak above it. A row is a (network, recipe) pair rather than a network — ResNet-50 has a row per recipe — and the recipe is the middle field of the job’s own name.

Table C-1 The Track 4 ImageNet-1k targets, their recipes and their job configs.

Target

Recipe

Job config

resnet34-imagenet-verified

default (the 2018 recipe)

r34-default-bf16-4gpu

resnet50-imagenet-verified

2018

r50-2018-bf16-4gpu

resnet50-imagenet-verified

a3 (RSB-A3, train@\(160\))

r50-a3-wxclip4x128-bf16-4gpu

mobilenetv2-imagenet-verified

default

mnv2-default-4gpu

efficientnet-imagenet-verified

default

enet-default-4gpu

convnext-imagenet-verified

default (the official recipe)

cnx-default-emabf16-4gpu

vit-imagenet-verified

default (DeiT-Ti)

vit-default-emabf16-4gpu

Every row has run. One chapter prints a pair from an earlier conf than the row trains today — ConvNeXt-T — and its marker names it. scripts/jobs/ also carries axis siblings that this table does not list — an fp32 peer of each of the ResNet-34, ResNet-50 2018, RSB-A3 and ViT rows, and RSB-A3 at \(8\times 64\) — which differ from their row in precision or in accumulation shape, never in the recipe, plus selftest, which exercises the supervisor without a GPU. Each config’s header says which it is.

This tier needs Python

ImageNet data does not sit in a directory the way MNIST and Imagenette do. It is streamed from tfds through a generated per-net shim, a Python script emitted from that net’s own reference TrainConfig, so the augmentation the verified trainer consumes is the augmentation its JAX reference trains on by construction, and scripts/shim_wiring_gate.py checks the pairing. Generate them before the first run:

scripts/gen_shims.sh

Each net names its own shim, and the driver refuses to start if the named file is absent.

Running one

Single device, on the driver’s own defaults:

LEAN_MLIR_MEM_FRACTION=0.97 .lake/build/bin/resnet34-imagenet-verified data

The defaults are the recipe: the mom256 render at batch \(256\), a peak learning rate of \(0.1\), \(90\) epochs. The one knob a single card needs is the allocator’s: at batch \(256\) the fp32 step peaks above the \(11.68\) GiB the PJRT shim reserves by default on a 16 GB card, and \(0.97\) reserves \(15.11\). Table C-2 is the rest.

Table C-2 The ImageNet drivers’ environment knobs.

Variable

Sets

Note

LEAN_MLIR_MEM_FRACTION

the device memory the shim reserves

\(0.97\) on a 16 GB card at batch 256

LEAN_MLIR_VARIANT

which render the driver loads

the batch is baked into the graph, not a runtime dimension

LEAN_MLIR_BATCH

the batch that variant was rendered at

a mismatch is a shape error at the first invoke

LEAN_MLIR_BASE_LR_U

the base learning rate, in millionths

100000 = 0.1; an integer because this toolchain has no String.toFloat?

LEAN_MLIR_EPOCHS

the schedule’s length

LEAN_MLIR_MAX_EPOCHS only caps a longer schedule, for a checkpointed prefix

PJRT_REPLICAS and LEAN_MLIR_REPLICAS

data parallelism: the shim’s client and compile options, and the driver’s data-parallel invoke

set only one and the run fails with “compiled for \(N\) replicas”; the job configs set both

LEAN_MLIR_LOWERER

xla or iree

collectives exist only on the PJRT path, so this tier is XLA-only

ResNet-50’s driver defaults to the AdamW rate \(0.001\) and its 2018 render is heavy-ball, so left unset there it under-steps by \(\sim \)100\(\times \), which looks like a broken render rather than a wrong knob. One card is the shape for a smoke test, not for the schedule. The four-card one, with every knob taken from the job’s own config, is lake run r34-default-bf16-4gpu once, and plan prints the wall-clock on file — the next section.

Running one for a day and a half

These are multi-day runs, so they go through a supervisor (scripts/supervise.sh) that owns the device list, the epoch budget and the restart policy, and the job’s own name is the command:

lake run r34-default-bf16-4gpu        # supervised: resumes, restarts on AER / heat / stall
lake run r34-default-bf16-4gpu plan   # the precheck and the wall-clock on file; runs nothing
lake run r34-default-bf16-4gpu once   # one foreground run with the job's env, no restarts
lake run imagenet                # every row's plan, in chapter order; runs nothing
lake run imagenet start          # the rows in order, each resuming from its checkpoint

lake run imagenet is the tier itself, the fourth of the four. Bare, it only plans, because its fourteen rows — the seven of Table C-1 and seven of the eight side quests of Table C-3 — are weeks of four-card time; start is the confirmation.

Side quests

Several chapters end in a variant that is rendered but is not a Track-4 runner, and the section heading says which of three kinds it is: a second recipe, a wider or deeper size, or an architecture the book reaches for once. They are collected here rather than in Table C-1 because they are side quests, not because they cannot start. All eight have job configs and launch like any Track-4 row. Seven ride in lake run imagenet right after their chapter’s row; the 100-epoch MobileNetV4 job has no lake script of its own and launches as scripts/supervise.sh mnv4-full-e100-4gpu. Each row’s section says where it stands.

Table C-3 The side-quest renders: target, variant, job and section.

Target

Variant

Job

Section

resnet50-imagenet-verified

a2

r50-a2-bf16-4gpu

§5.9

resnet50-imagenet-verified

a1

r50-a1-bf16-4gpu

§5.9

mobilenetv4-imagenet-verified

full, 100 ep

mnv4-full-e100-4gpu

§6.6

mobilenetv4-imagenet-verified

full, 500 ep

mnv4-full-4gpu

§6.6

convnext-s-imagenet-verified

—

cnxs-default-emabf16-4gpu

§8.6

convnext-b-imagenet-verified

—

cnxb-default-emabf16-4gpu

§8.6

vit-s-imagenet-verified

—

vits-default-emabf16-4gpu

§9.7

vit-b-imagenet-verified

—

vitb-default-emabf16-4gpu

§9.7